As the scale and density of the chip increases due to the smaller size of semiconductor devices (the shrinking of transistor dimensions), so do the time required for performing selection tests (such as wafer test in the previous process and the final test after package process) and test cost, making the reduction of product costs difficult. The increase in the scale of the chip translates into a growing number of transistors per chip thereby increasing the number of combinations. The increase in the density of the chip translates into an increase in the number of transistors per unit area, thereby increasing the defect probability per unit area, complicating the physical phenomena, and increasing the number of types of defects. Further, due to higher integration and greater functionality, a longer period of time is required for the generation of a test pattern by for instance an ATPG (Automatic Test Pattern Generator).
As shown in FIG. 4, conventionally a technique that runs a test on a plurality of chips to be measured (a.k.a. DUT: Device Under Test) in parallel is used in order to reduce the test time. A plurality of input/output ports (pairs of drivers and comparators; a.k.a I/O channels or I/O pins) of a tester 1 (Automatic Test Equipment) are divided into a plurality of sections, a device to be measured is connected in each section, and the single tester 1 performs a parallel test on a plurality of chips to be measured 10-1 to 10-3 simultaneously. When functional testing is performed, a test pattern (force pattern) is supplied in parallel to the plurality of chips to be measured 10-1 to 10-3 from a separate driver (not shown in the drawing) of each section, outputs of the plurality of chips to be measured 10-1 to 10-3 are compared in parallel with an expectation value pattern by a comparator of each section, and then a result (pass or fail) is determined.
Further, regarding BOST (Built Out Self Test) used in the present invention, which will be described later, for instance Patent Document 1 can be referred to Patent Document 1 discloses a test apparatus that conducts a pattern dependency test and timing dependency test using semiconductor chips for testing such as BIST (Built In Self Test) and BOST. The invention disclosed in Patent Document 1 does not test chips to be measured and chips for testing in parallel.
[Patent Document 1]    Japanese Patent Kokai Publication No. JP-P2003-16799A